The present disclosure relates to integrated circuit devices and methods of forming integrated circuit devices. Three-dimensional (3D) packages including a plurality of semiconductor chips mounted on a single semiconductor package may be implemented for integrated circuit devices. Accordingly, through-silicon-via (TSV) technology for forming a vertical electric connection through a substrate or a die may be beneficial. Copper (Cu) diffusion in a TSV structure including a Cu contact plug, however, may cause performance and reliability problems for 3D packages.